High-Speed and Low-Power Stacked Dynamic Comparator for ADC

This work presents the design and implementation of a Stacked Dynamic Comparator for high-speed analog and mixed signal applications like ADCs. A feedback mechanism is introduced in the design where the output nodes are connected back to the tail transistors during the pre-charge phase. This limits the current flow during the pre-charge phase and makes the SDC consume less power and parallelly achieve high-speed. This leads to reduced Power-Delay Product (PDP). The SDC also incorporates stacking of regenerative latch resulting in reduced leakage power. The parasitic ground-path resistance is also reduced to decrease the latch delay. The enhanced power efficiency and PDP makes the SDC a promising solution for high-speed and low-power applications. The performance of the SDC has been evaluated by simulating the design in Cadence Virtuoso tool using the gpdk180 library.