Deep&Wide: Achieving Area Efficiency in Scalable Approximate Accelerators
Automatic synthesis of approximate accelerators remains a challenging problem owing to extremely large design space and high verification costs for evaluating intermediate design candidates. Existing frameworks typically employ searchbased strategies to explore the design space. While some frameworks aggressively prune candidate configurations to reduce runtime, leading to prematurely eliminating high-quality solutions, others use a learning based approach for design space exploration with an increased runtime cost. In this work, we propose an advanced Design Space Exploration (DSE) approach that incorporates a refined, cost-aware selection and expansion strategy to enable a more balanced and effective traversal of the search space. Our method builds upon an existing learning-based state-of-the-art technique to improve the accuracy and quality of tradeoffs, especially for large-scale accelerators. Experimental results demonstrate that our proposed approach achieves comparable area and power savings for small to medium-scale benchmarks while significantly outperforming the state-of-the-art approaches on larger circuits with up to 9% additional area savings with almost no runtime overhead.
Authors
- Thorsten Jungeblut (ORCID: https://orcid.org/0000-0001-7425-8766)
- Marco Platzner (ORCID: https://orcid.org/0000-0002-6893-063X)
- Qazi Arbab Ahmed (ORCID: https://orcid.org/0000-0002-1837-2254)
- Muhammad Awais (ORCID: https://orcid.org/0009-0007-1443-4773)
- Hassan Ghasemzadeh Mohammadi
- Farjana Jalil
Institutions
- Hochschule Bielefeld (DE)
- Paderborn University (DE)
- Ibeo Automotive Systems (Germany) (DE)
Publication Details
- Published
- 2025-06-23
- DOI
- https://doi.org/10.1109/dsn-w65791.2025.00048
- Citations
- 1
- Primary Topic
- Low-power high-performance VLSI design
- Type
- article
- Field-Weighted Citation Impact
- 0.73