Efficient Clock Gating in Differential Flip-Flops: A GDI-Based Approach

In low-power and low-voltage digital applications, flip-flop design plays a crucial role in optimizing power consumption and operational reliability. The existing CMOS Static Contention- Free Differential Flip-Flop (SCDFF) employs footed differential latches to achieve static and contention-free operation without unnecessary internal clock transitions. This design provides reliable performance while maintaining the same silicon area as a traditional Transmission-Gate Flip-Flop (TGFF). Unlike conventional Adiabatic Clocked Flip-Flops (ACFF), SCDFF utilizes gate connections instead of diffusion connections, ensuring complete static and contention-free functionality. In the proposed method, a GDI-based SCDFF is introduced, leveraging the Gate Diffusion Input (GDI) technique combined with an AND-based clock gating mechanism to further enhance flip-flop efficiency. By integrating a GDI-AND structure, the design minimizes contention issues while improving power efficiency and operational stability. This approach significantly enhances flip-flop performance, making it highly suitable for energy- efficient, low-voltage applications. The proposed GDI-SCDFF demonstrates superior power savings and robustness, offering a promising alternative for modern digital circuit design.