Energy-Efficient and DPA Attack Resilient S-Box Design for Secure Edge AI Devices Using 8T-SRAM Computing-in-Memory

Side-channel attacks present a considerable risk to the security and trustworthiness of Edge AI devices as the use of AI-based hardware applications continues to increase. In this work, a novel 8T-SRAM Computing-in memory (CiM) S-box for lightweight SLIM cipher design has been developed using Negative Capacitance FETs (NCFETs) to enhance energy efficiency and protect against Differential Power Analysis (DPA) attacks. The proposed CiM architecture's reconfigurability, when paired with the NCFET's distinct steep slope properties in logic gates, contributes to improving the DPA resistance and energy efficiency of the overall S-box design. Based on simulations, it was discovered that the proposed NCFET-based 8T-SRAM Computing-in-Memory (CiM) S-box for the SLIM cipher exhibits approximately 3.8 times less energy usage when compared to the non-CiM S-box design at a voltage of 0.5V. The security analysis of the NCFET based 8T-SRAM based CiM S-box design against DPA attacks exhibits 32x increase in the attacker's effect ratio and ~43.4x improvement in the security power delay (SPD).