Multi-Precision SIMD Posit Systolic Array Accelerator for Deep Learning

In the domain of deep neural network (DNN) accelerators, achieving an optimal balance between precision, performance, and efficiency is crucial, especially for edge AI applications with demanding computational requirements in resource-limited environments. This research presents innovative single instruction multiple data (SIMD) Posit Processing Engines (PEs) based accelerator for deep learning. The PEs enable multiple precisions, viz. 8, 16 and 32 bits. The accelerator's multiple-precisions setting enhances both hardware efficiency and adaptability. The design has been validated on the Virtex-7 FPGA, demonstrating significant improvements in resource utilization, achieving a 38% reduction in Slice-LUTs and a 90% reduction in Flip-Flop usage compared to traditional architectures supporting only 8-bit, 16-bit or 32-bit based computations. The proposed design mitigates the usage of DSP blocks in FPGA, thereby simplifying hardware and improving efficiency. Operating at 100 MHz, the proposed architecture features a single multi-precision activation function (AF) outside the systolic array, supporting sigmoid, tanh, or Rectified Linear Unit (ReLU). ReLU is used for evaluation and to demonstrate the flexibility and performance of the system. The design articulates multi-precision SIMD Posit, achieving notable improvements in resource utilization and performance compared to the current state-of-the-art designs offering a scalable and efficient solution for various DNN acceleration applications.