Titan Bound: The FPGA SoC Design of the Navigation Coprocessor Controller

This paper describes the architecture and verification of the Navigation Coprocessor Controller (NCC) FPGA and its soft processor implemented for NASA's New Frontiers Dragonfly mission to Titan. NCC is a Peripheral Component Interconnect (PCI) target to Flight Software (FSW) and resides on the Navigation Coprocessor Board (NCP). Some of the key functionalities for NCC include sending commands to, and receiving telemetry from, the Rotor Drive Electronics (RDE) on a precise interval., providing an interface to the Onboard Vision Processing (OVP) on FPGA, recording of raw images and Light Detection and Ranging (LiDAR) relief map to NAND Flash, booting of components on the NCP, scrubbing of OVP, and sending commands to the NavCam and LiDAR over universal asynchronous receiver / transmitter (UART). NCC contains an Advanced Microcontroller Bus Architecture (AMBA) that is segmented into two portions connected via an advanced high-performance bus AHB to AHB bridge in order to separate frequent traffic from FSW and OVP. The team used a mixture of traditional and modern verification practices to verify the NCC. Many designers verified their modules individually in the NCC using traditional very high speed integrated circuit (VHSIC) Hardware Description Language (VHDL) testbenches. The top-level simulations used the modern Universal Verification Methodology Framework (UVMF) from Siemens to establish a common framework to test the complex design of the NCC, and to allow both flexibility and scalability as the NCC design evolves.