High-Speed Approximate Adder Design Through Charge Recovery Logic and Hybrid Low Power Technique

In this paper we have presented a ground breaking approach to the development of a high-speed approximate adder with advanced security features. The proposed design incorporates adiabatic logic through the utilization of the LECTOR approach and POWER GATING TECHNIQUE, aiming to optimize both speed and security in the approximate addition process. Adiabatic logic ensures energy-efficient computations, while the LECTOR methodology enhances the overall security of the adder. The abstract provides an overview of the novel methodology, design considerations, and the anticipated benefits of integrating high-speed approximation with adiabatic logic along with the LECTOR & POWER GATING approach for heightened security. This research contributes to the forefront of secure and efficient arithmetic circuitry, holding promise for diverse applications. Simulation results are obtained using EDA tool T -SPICE incorporating 45 nm technology file. The proposed technique is having average power improvement of 25.1 % and average delay improvement of 51.8%, when compare to existing technique.