K_Means Clustering for Scan Chain Stitching

Scan based testing is crucial in modern Integrated Circuits (ICs) to identify the manufacturing defects and shows the reliability of digital designs. However, during testing, the continuous switching of flip-flops increases power consumption. Traditional scan chain stitching methods mainly focus on fault detection and do not consider scan shift power optimization as their main factor. However, it is very essential to have a method which can reduce power consumption without disturbing the test fault coverage. The proposed work introduces a novel machine learning approach using K_means clustering to optimize the length of scan chains in the ICs. Scan chain stitching is an important step in the Design for Testability (DFT) process, where flip-flops are arranged based on their controllability values during testing. By applying K_means clustering, the reduction in scan shift power consumption is possible without compromising the test coverage which makes the scan-based testing more reliable.