Comparative Analysis of 6T, 8T, and 10T SRAM Architectures: A Study on Power, Noise Margin, and Leakage Current

Modern computing requires Static Random Access Memory (SRAM) architectures that balance power efficiency and reliability. Through 45nm CMOS simulations, we compare 6T, 8T, and IOT SRAM cells, revealing: the IOT single-ended design reduces leakage current to 66.58 pA (99.9% lower than 6T's <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$70.72 \mu \mathrm{A}$</tex>.), while 8T cells triple the static noise margin to 0.499 V. These results yield clear design guidelines: 6T cells (<tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$84.86u\mathrm{W}$</tex> active power) optimize IoT edge devices, 8T designs (6.527 mW) balance general computing needs, and IOT configurations (0.503 V SNM, 79.9 pW leakage) secure mission-critical systems. Our framework simplifies SRAM selection by quantifying three crucial parameters: SNM (stability), leakage power (standby efficiency), and active power consumption, all of which are critical for AI accelerators and advanced nodes. The findings equip designers with quantitative insights for architecture selection in next-generation computing systems.