Physical Verification and Validation of the Digital Analog and Mixed-Signal Designs for the SCL 180nm CMOS Technology

This paper provides a detailed overview of the essential tapeout checks required for successfully designing and tape-out of Digital, Analog, and Mixed-Signal VLSI circuit designs using SCL 180nm technology. It serves as a comprehensive guide for designers, offering critical insights and necessary inputs for preparing and submitting designs to SCL foundry. This resource aims to ensure clarity and facilitate the seamless execution of tapeout processes, thereby enhancing the overall quality and reliability of integrated circuit fabrication for the SCL 180nm Process Design Kit (PDK).