Approximate Parallel Prefix Adders for Image Processing Applications

Approximate computing has emerged as a powerful solution for error-tolerant applications where perfect accuracy is not mandatory. Among arithmetic units, parallel prefix adders (PPAs) are preferred for high-speed operations due to their efficient carry generation and propagation. This work proposes novel approximate prefix operations (AxPOs) and integrates them into four PPA architectures. Three new designs are introduced, leveraging logic simplifications using Feynman and OR gates in the approximate sections to reduce circuit complexity. Experimental results, synthesized using Cadence Genus on 45nm CMOS technology, show that the proposed designs achieve up to 32.1% area reduction, 29.8% lower power consumption, and 22.98% delay improvement compared to existing approximate PPAs. In image sharpening applications, the proposed Ladner-Fischer adder delivers a PSNR of 24.3 dB versus 20.1 dB for the baseline, indicating improved visual quality. These trade-offs between accuracy and hardware efficiency make the designs ideal for low-power, high-performance VLSI systems in real-time multimedia applications.