32-Bit RISC-V Processor with Switchable Floating Point ALU

The 32-bit RISC-V processor with a five-stage pipeline and a switchable floating-point ALU (FPU) is a high-performance and power-efficient computing architecture designed for modern applications requiring both integer and floating-point computations. This paper explores the RISC-V instruction subsets (RV32I and RV32F), detailing how the processor efficiently manages arithmetic, logical, memory, and control operations. The floating-point ALU, compliant with the IEEE 754–2008 standard, dynamically switches between integer and floating-point operations, ensuring optimized resource utilization and reduced execution latency. The processor's pipeline structure, along with hazard handling mechanisms for data, control, and structural hazards, enables seamless execution with minimal stalls. The floating-point switching mechanism enhances computational efficiency by directing integer operations to the integer ALU and floating-point operations to the FPU, reducing power consumption and improving performance. This architecture is particularly suited for scientific computing, machine learning, digital signal processing (DSP), and embedded systems, where high-speed floating-point arithmetic is essential. Additionally, advanced techniques such as operand forwarding, out-of-order execution, and fused multiply-add (FMA) operations further optimize floating-point performance. The modular and open-source nature of RISC-V makes it a versatile and scalable processor architecture for edge AI, autonomous systems, IoT, and cloud-based high-performance computing (HPC) applications. This study highlights the efficiency, scalability, and future potential of the 32-bit RISC-V processor in emerging computational workloads.