Area and Power Efficient, Scalable Offset Compensation Scheme for High-Speed, High Resolution Time Interleaved ADC

This paper proposes an area and power efficient offset compensation technique for the comparators of 8-bit, 8-way time-interleaved SAR ADC. The ADC operates at 8Gsps and supports 50 Om V of differential peak-to-peak dynamic range. The offset DAC scheme offers very high resolution of less than 400uV « 0.25LSB of ADC) and range of +/-lOOmV considering 5 sigma of process and mismatch variation. The proposed scheme enables sharing of offset DAC across 8 interleaved sub-ADCs resulting in improved efficiency in terms of occupied area and consumed power. The design is implemented in Intel 3nm FinFET technology and operates from 0.85V of supply. Averaged area and power consumption of the shared offset DAC scheme per sub-ADC are 600um2 and 85uW respectively. The offset compensation scheme is scalable as it can be extended to a higher speed ADC realized by higher number of Interleaving stages. The ADC is designed for wireline P AM-X receiver supporting automotive applications.