ASIC vs FPGA Realization of a Cryptographically Secure Random Number Generator Using Chaotic Map

This research involves the implementation of a chaos-based pseudo-random number generator (PRNG) based on Hardware Description Language (HDL) and implementation over FPGA and ASIC platforms. The chaotic function based on the logistic map is used to generate pseudo-random numbers, which are important in cryptographic uses, specifically in the field of cryptographically secure pseudo-random number generators (CSPRNGs). One of the major challenges that are involved in hardware implementation include converting an algorithmic model optimized in MATLAB to an efficient HDL implementation, while simultaneously ensuring optimal numerical representation and architectural fidelity. While field-programmable gate arrays (FPGAs) enjoy the advantage of reconfigurability and fast prototyping, they could be linked to increased power consumption due to routing overhead and idle logic. However, ASIC implementations deliver optimized speed, less power consumption, and less spatial requirements; however, they are fixed after production. To evaluate performance, the design is synthesized and implemented over both FPGA and ASIC platforms, and tests are carried out in terms of power consumption, area, and timing efficiency. Additionally, the performance of the PRNG is tested using the NIST SP 800–22 statistical tests, while hardware efficiency is tested using power analysis. This research clarifies the trade-offs in FPGA and ASIC implementations and provides useful insights into choosing the most appropriate platform for chaos-based cryptographic schemes.