Investigation of Nanoscale Bonding-Based Complementary FETs

In this article, the nanoscale bonding-based complementary field-effect transistor (B-CFET) is proposed as a high-performance alternative to sequential CFETs (S-CFETs) for next-generation technology nodes. Unlike S-CFETs, which suffer from thermal budget constraints that lead to junction abruptness degradation, B-CFET mitigates these issues by employing low-temperature bonding techniques for CFET integration. This approach enables the use of heterogeneous channel materials and allows independent nMOS/pMOS optimization. To assess its performance feasibility, B-CFET is compared with S-CFET. 3-D TCAD simulations indicate that, when accounting for the junction abruptness degradation of S-CFET’s bottom transistor due to dopant diffusion (assuming an increase of 1 nm per decade), B-CFET achieves an 11.1% improvement in operating frequency at the same leakage power (<italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">f</i><sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><roman>ISOLEAK</roman></sub><roman xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">)</roman> compared to S-CFET. Although additional bonding bump layers extend vertical interconnects or cause misalignment and void formation, potentially increasing external resistance, segmented resistance analysis indicates that these factors have a negligible impact on overall performance. Even under extreme conditions, where the bonding resistance increases significantly from 17.5 to 60.7 Ω (a 247% increase), B-CFET exhibits excellent robustness, with only a 1.0% degradation in <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">f</i><sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><roman>ISOLEAK</roman></sub>. This minimal degradation highlights the negligible influence of (<italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">R</i><sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><roman>BUMP</roman></sub><roman xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">)</roman> on overall performance and reinforces its potential as a scalable and resilient architecture for future CFET technologies.

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Publication Details

Journal
IEEE Transactions on Electron Devices
Published
2025-07-14
DOI
https://doi.org/10.1109/ted.2025.3585900
Primary Topic
Advancements in Semiconductor Devices and Circuit Design
Type
article
Field-Weighted Citation Impact
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article

Investigation of Nanoscale Bonding-Based Complementary FETs

Jongwook Jeon, Kee-Won Kwon, Seung Kyu Kim, J.J. Kim
3 links
IEEE Transactions on Electron Devices
Advancements in Semiconductor Devices and Circuit Design
article

Investigation of Nanoscale Bonding-Based Complementary FETs

Jongwook Jeon, Kee-Won Kwon, Seung Kyu Kim, J.J. Kim
article en

Abstract

In this article, the nanoscale bonding-based complementary field-effect transistor (B-CFET) is proposed as a high-performance alternative to sequential CFETs (S-CFETs) for next-generation technology nodes. Unlike S-CFETs, which suffer from thermal budget constraints that lead to junction abruptness degradation, B-CFET mitigates these issues by employing low-temperature bonding techniques for CFET integration. This approach enables the use of heterogeneous channel materials and allows independent nMOS/pMOS optimization. To assess its performance feasibility, B-CFET is compared with S-CFET. 3-D TCAD simulations indicate that, when accounting for the junction abruptness degradation of S-CFET’s bottom transistor due to dopant diffusion (assuming an increase of 1 nm per decade), B-CFET achieves an 11.1% improvement in operating frequency at the same leakage power (<italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">f</i><sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><roman>ISOLEAK</roman></sub><roman xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">)</roman> compared to S-CFET. Although additional bonding bump layers extend vertical interconnects or cause misalignment and void formation, potentially increasing external resistance, segmented resistance analysis indicates that these factors have a negligible impact on overall performance. Even under extreme conditions, where the bonding resistance increases significantly from 17.5 to 60.7 Ω (a 247% increase), B-CFET exhibits excellent robustness, with only a 1.0% degradation in <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">f</i><sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><roman>ISOLEAK</roman></sub>. This minimal degradation highlights the negligible influence of (<italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">R</i><sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><roman>BUMP</roman></sub><roman xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">)</roman> on overall performance and reinforces its potential as a scalable and resilient architecture for future CFET technologies.

IEEE Transactions on Electron DevicesVol. 72(9)
Sungkyunkwan University (KR)
Samsung
Openalex Percentile: Top 85%
Advancements in Semiconductor Devices and Circuit Design
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