Modeling, Digital Control, and Design Techniques in a Novel Cascaded 48-to-PoL Architecture for Fast Transient Response and Enhanced Stability

This paper presents accurate modeling, digital control architectures, and design methodologies for a novel cascaded DC-DC converter for 48V-to-point-of-load (PoL) applications. Using a non-isolated intermediate architecture (IBA), the 48 V input is converted to 12 V, which is further converted to 1 V in the PoL stage using a series capacitor buck (SCB) converter. The PoL converter is tightly regulated and modeled as a constant power load (CPL), introducing a negative incremental impedance effect that influences the stability of the IBA. Discrete-time (DT) large- and small-signal models are derived to accurately capture system dynamics by incorporating parasitics and sampling delays for cycle-by-cycle stability analysis. A voltage-mode digital phaseshift modulation (DPSM) is employed to control the IBA, which is designed using a hybrid approach by combining reduced-order and higher-order small-signal models to balance complexity and accuracy. Digital current mode control is employed for the PoL stage, which is designed using a state feedback approach to ensure fast dynamic performance throughout load variations. Step-bystep controller design guidelines are provided for the cascaded architecture to ensure stability and robustness under dynamic loads. The proposed approach is validated through simulation and experimental results for 48V-to-1V power conversion. Comparative analysis demonstrates enhanced transient response and stability, confirming the effectiveness of the proposed design.