Scalable FPGA Implementation of a Reliability-Based Direct Turbo Decoder for Short Block Codes

Turbo codes are widely used in satellite and mobile communication systems for their strong error-correcting performance. However, conventional iterative decoders such as Log-MAP suffer from high complexity and exhibit error floors in short block-length regimes. To address this, a Reliability-Based Compact Direct Decoder (RCODD) algorithm has been proposed as a non-iterative alternative that leverages encoder state information and demodulator reliability metrics for efficient decoding. This paper presents the first hardware implementation of the RCODD algorithm on an FPGA, featuring a serial architecture optimized for minimal memory usage and logic complexity. Synthesized on a Zynq-7010 FPGA, the design achieves a BER of 0.7×10<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">−4</sup> at 2 dB SNR for a 16,000-bit stream while consuming only 49% of available BRAM and 56% of LUTs. A 4-way parallel version of the architecture is also proposed and simulated, demonstrating a 3.8× reduction in latency while preserving decoding performance. Additionally, a fixed-point quantization study confirms that a 16-bit representation of reliability values introduces negligible error, offering further scope for area and power optimization. Comparative analysis with existing turbo decoder designs shows that the proposed RCODD-based architecture is uniquely positioned to serve low-power, high-reliability applications such as satellite telecommand systems, while remaining scalable to higher-throughput needs.