Design of a D-Band Multiply-by-9 Frequency Multiplier Chain in 16 nm p-FinFET Technology With Waveform Modeling

This work presents the design and analysis of a compact D-band ×9 frequency multiplier chain, using TSMC 16nm technology with the RF p-FinFET device. The unique high <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$\mathbf {f_{max}}$</tex-math></inline-formula> feature of the p-FinFET device sets the foundations for this design. To accommodate the short-channel effects in the FinFET devices, a time domain double-clipped piece-wise linear model is proposed to analyze the current waveform of the frequency tripler, which proves to be accurate in predicting the harmonic generation behavior of FinFET by comparing with the simulation. The optimal load impedance and the matching conditions at 3f<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$_{0}$</tex-math></inline-formula> are also examined to improve the efficiency. The frequency multiplier chain consists of an inductor-less active balun for single-to-differential conversion and mismatch compensation, two frequency tripler cells, an inter-stage amplifier, and a two-stage driving amplifier (DA) at the output. The proposed model was applied to find the optimal bias condition when designing the frequency triplers. The proposed multiplier was measured under two bias conditions; the first achieves a conversion gain of 1.6 dB, a <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$\mathbf {P_{sat}}$</tex-math></inline-formula> of -2.8 dBm and a harmonic rejection ratio (HRR) of 44 dBc while consuming 58 mW DC power. The second bias point achieves a higher conversion gain and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$\mathbf {P_{sat}}$</tex-math></inline-formula> at 4.7 dB and 1.8 dBm with 102 mW DC power. The multiplier chip occupies a core area of only 0.068 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$\mathbf {mm^{2}}$</tex-math></inline-formula> and the phase noise degradation is 19.8 dB at 1-MHz frequency offset.