Systematic Investigation of Wafer-Level Performance in AlScN-Based PMUTs

The systematic investigation of wafer-level performance in AlScN-based PMUTs is crucial for high-yield mass production and application development. In this work, pinned structures with 600 μm and 1000 μm diaphragm diameters (Pinned 600U, Pinned 1000U) were prepared based on an 8-inch SOI wafer. The optimization of MEMS process parameters and the analysis of resonant behavior across multiple wafer-level devices based on the neutral axis model have been carried out systematically. The MEMS process parameters included the distribution of piezoelectric film thickness, piezoelectric film stress, diaphragm diameter and residual silicon oxide after diaphragm release across the wafer. The Pinned 600U exhibited greater wafer-level performance uniformity by optimizing key parameters that were mentioned. The uniformity of within-wafer and wafer-to-wafer were achieved less than 1.5% and 4.5% respectively in resonant frequency and electromechanical coupling coefficient. The LDV tests showed a highly consistent (1.56%) amplitude in resonant frequency across devices. High wafer-level performance uniformity enables high-yield mass production and thereby reducing costs. This study offers valuable wafer-level guidance, facilitating both high-yield mass production and the performance enhancement of PMUTs and other MEMS devices based on AlScN, particularly for array applications.