Implementation and Optimization of Object Detection on FPGA-Based CPU+NPU Heterogeneous System

With the rapid development of Artificial Intelligence (AI), deep learning algorithms are getting larger and larger, and traditional general-purpose computing platforms (e.g., CPUs and GPUs) have limitations in terms of energy efficiency ratio, latency, and customizability. In this study, we propose an FPGA-based CPU+NPU heterogeneous system aimed at optimizing and accelerating the processing efficiency of object detection algorithms and design a dedicated object detection post-processing non-maximum suppression (NMS) circuit module, which greatly improves the post-processing performance. Experimental results show that our system reduces latency by a factor of <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\mathbf{1 4 9}$</tex> compared to a CPU implementation of the Intel E5 2620 V4 and offers several to several tens of times energy advantages over both GPU and other FPGA designs. These quantitative data demonstrate the significant advantages of our approach in terms of processing speed and energy efficiency, providing strong technical support for the future deployment of efficient object detection models on edge computing devices.