An Optimized Retiming-based FIR Filter Architecture using Efficient Multipliers and Adders

Introduction: An efficient higher-order filter architecture is designed and implemented for ECG signal processing applications. To prune the latency of the architecture, the retiming technique is considered for the design of less memory type Finite Impulse Response (FIR) filter architecture. The optimized multipliers and adders are key blocks in the filter architecture to increase the latency and Power Consumption (PC). Methods: In this regard, an optimized Radix-4 Booth Multiplier (RBM) is designed using a modified booth encoder and selector blocks along with the proposed improved version of Square Root Carry Select Adders (SRCSLA). The design metrics of the multiplier, which is used to multiply the inputs and coefficients of the filter also improved by using the proposed SRCSLA. For the proposed SRCSLA, The Carry Look Ahead (CLA) adder and Carry Skip Adder (CSA) are combined and modified for the proposed SRCSLA. Different bit size-based SRCSLA adders are implemented for the proposed multiplier architecture and to accumulate the final filter output. The adder structure speed is improved by modified carry-producing and propagating blocks. The retiming- based FIR filter architecture with order N = 32 is coded by HDL and synthesis is carried out using Genus synthesis tools in 45nm CMOS technology provided by CADENCE. Results: Area Complexity (AC), Delay Complexity (DC), and PC are estimated by the reports generated by the software tool. The trade-off design metrics Area-Delay-Product (ADP) and Power- Delay-Product (PDP) are also estimated and correlated with the conventional filter structures and existing filter architectures. Discussion: The proposed higher-order FIR filter architecture demonstrates significant improvements in latency and power efficiency for ECG signal processing by leveraging retiming techniques and optimized arithmetic blocks. The integration of an enhanced RBM with a novel SRCSLA, which combines features of CLA and CSA, results in faster and more power-efficient computation. Synthesized in 45nm CMOS using Cadence Genus, the design shows reduced Area, Delay, and Power. However, the complexity of SRCSLA logic and increased design overhead for retiming may present scalability and implementation challenges for ultra-high-order filters. Conclusion: The proposed work is better comparatively existing works using the retiming concept.