Direct Observation of Etching‐Induced Inhomogeneous Strain in Advanced Si/SiGe Stack for Gate‐All‐Around Transistor

Abstract The gate‐all‐around field‐effect transistor (GAAFET) provides enhanced electrostatic control and improved current driving capabilities, positioning it as a promising candidate for fin field‐effect transistor (FinFET). However, the SiGe selective etching process‐induced strain affects the current transportation property along the channel, while the morphology and strain profiles at atomistic scale remain unclear. In this study, the anisotropic etching of the Si/SiGe stack and the selective isotropic etching of the SiGe process is carried out. It is discovered that uneven etching rates in lateral and vertical dimensions of the stack induce non‐uniform etching depth within the SiGe layer. High‐resolution high‐angle annular dark‐field (HAADF) imaging in scanning transmission electron microscopy (STEM) with strain analysis technique shows that the strain profile in the Si stack is inhomogeneous, and the bottom layer of the nanosheet suffers the highest strain. Technology computer‐aided design (TCAD) simulation results at the device level indicate that such inhomogeneous strain profiles reduce the drain current. The findings provide direct proof at the atomistic scale for high‐performance manufacturing of advanced GAAFET.