Analysis of Approximate Multipliers using FinFET

In error-tolerant applications such as multimedia processing and machine learning, approximate computing has emerged as a promising strategy for low-power designs. Multiplier is one of the most power consuming circuit used in digital computing devices. This work analyses the performance efficiency of six unsigned approximate multipliers FinFET technology. The approximate multipliers are implemented for 4-bit operand. These designs are implemented in CMOS and FinFET technologies. The designs are analyzed by the following metrics: power consumption and critical path delay. Multiplier-3 is the best performing design with critical path delay of <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$1.5\mu \mathrm{S}$</tex> and power consumption of <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$3.88\mu \mathrm{W}$</tex> in CMOS technology and critical path delay of <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$0.5\mu \mathrm{S}$</tex> and power consumption of 400.2nW. Multiplier-3 design improves the power dissipation by 96.61% and Delay by 65.71% compared to exact multiplier in CMOS technology. It also improves the power dissipation by 89.54% and Delay by 85.73% compared to exact multiplier in FinFET technology.