Design and implementation of SMCC based on SIMT processor

As the demand for parallel computing continues to grow, SIMT (Single Instruction Multiple Thread) architecture has become the mainstream architecture for high-performance graphics processors (GPUs) due to its excellent thread scheduling mechanism and throughput capability. In this paper, we design and implement a shareable multi-channel Cache architecture based on the independently designed SIMT stream multiprocessor to cope with the access conflicts and performance bottlenecks faced by the traditional single-channel Cache in multi-core parallel computing. Supporting four-channel parallel access, the L1 Cache introduces a split-bank structure and a cross-switch network, combined with a configurable replacement algorithm and a dynamic request splitting and merging mechanism, which significantly improves the Cache hit rate and data transfer efficiency. Through functional simulation verification and targeted hit rate test, the results show that the architecture can correctly handle multiple access types under complex mixed requests with a hit rate of 94.83%, which verifies the effectiveness and scalability of its design.