Transient Model of Series-Connected SiC Mosfets Considering Inter-Device Coupling Effects

Enhancing power density and achieving lightweight are key trends in high voltage and high power applications, such as flexible DC transmission and DC distribution technologies. Series-connected SiC MOSFETs effectively increase voltage withstand levels, providing a reliable method for improving the power density of high-voltage, high-power converters. However, issues such as dynamic voltage imbalance and differences in voltage overshoot spikes are severe, with the latter causing damage to power devices during overload or short-circuit current turn-off. Un-balanced parasitic capacitances and inductances, particularly gate-to-power ground (<tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$C_{g p}$</tex>) and drain-to-power ground (<tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$C_{d p}$</tex>) capacitances, are major contributors to these problems. However, state-of-the-art research fails to consider the coupling effects of the parasitic capacitances between the devices. This paper explores the coupling effects of <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$C_{g p}$</tex> and <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$C_{d p}$</tex> between cascaded SiC MOSFETs and proposes a simplified transient circuit model based on Miller's feedback theorem. Measurement results show the proposed model achieves a maximum error of 28.3 % for dv/dt prediction and 17.5 % for voltage overshoot, effectively predicting voltage imbalance and overshoot spikes. It offers a valuable tool for improving the reliability of series-connected SiC MOSFETs.