SiC DMOSFET Real Wafer Level HTRB and HTGB Evaluation

Since 1990s, Silicon Carbide (SiC) was considered as important semiconductor materials for high-power and high-temperature applications due to their superior properties compared to silicon. However, evaluating the long-term reliability of SiC devices under extreme conditions remains critical with conventional packaged level testing approach. This paper presents Wafer Level (WL) reliability evaluation results of SiC double-implanted metal-oxide semiconductor field-effect transistor (DMOSFET) focusing on High Temperature Gate Bias (HTGB) and High Temperature Reverse Bias (HTRB) testing with threshold voltage monitoring (Vth). The evaluation result has showed 500 sites have been assessed successfully. The works demonstrated true wafer level measurement setup with special probe pins directly touching on probe pads without wafer backgrinding, wafer dicing and ceramic or plastic packaging processes at all.

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Publication Details

Published
2025-03-24
DOI
https://doi.org/10.1109/icmts63811.2025.11068904
Primary Topic
Silicon and Solar Cell Technologies
Type
article
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SiC DMOSFET Real Wafer Level HTRB and HTGB Evaluation

Ng Hong Seng, Wei Lin, Tan Ai Heong, Beh Shun Xiar et al.
3 links
Silicon and Solar Cell Technologies
article

SiC DMOSFET Real Wafer Level HTRB and HTGB Evaluation

Ng Hong Seng, Wei Lin, Tan Ai Heong, Beh Shun Xiar, Lee Johnny
article en

Abstract

Since 1990s, Silicon Carbide (SiC) was considered as important semiconductor materials for high-power and high-temperature applications due to their superior properties compared to silicon. However, evaluating the long-term reliability of SiC devices under extreme conditions remains critical with conventional packaged level testing approach. This paper presents Wafer Level (WL) reliability evaluation results of SiC double-implanted metal-oxide semiconductor field-effect transistor (DMOSFET) focusing on High Temperature Gate Bias (HTGB) and High Temperature Reverse Bias (HTRB) testing with threshold voltage monitoring (Vth). The evaluation result has showed 500 sites have been assessed successfully. The works demonstrated true wafer level measurement setup with special probe pins directly touching on probe pads without wafer backgrinding, wafer dicing and ceramic or plastic packaging processes at all.

Singapore Institute of Technology (SG), X-Fab (Germany) (DE), Quality and Reliability (Greece) (GR), X-Fab (United States) (US)
Openalex Percentile: Top 85%
Silicon and Solar Cell Technologies
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SiC DMOSFET Real Wafer Level HTRB and HTGB Evaluation — Ng Hong Seng, Wei Lin, et al. · (2025) | TGRS Research Map | TGRS