Layout experiments and test structures to characterize Local Layout Effects due to mechanical stress in FinFET transistors

This paper presents a characterization approach to study Local Layout Effects (LLEs) in FinFET devices. Since mechanical stress is commonly used as a mobility booster in modern transistors, layout-induced stress modulation will cause changes in performance. To investigate devices sensitivities and magnitude of variation a set of test structures with a broad range of Design of Experiment (DoE) factors is proposed, focusing on two layout features: FinFET isolation (diffusion break) and Gate Cut isolation. The test structures were deployed on 7nm test chip as part of PDF Characterization Vehicle CV® and electrical results showed that the magnitude of investigated LLEs could be as high as 13%. TCAD simulation study performed on the designed test structures confirmed that the performance variability can be explained by modulation of the mechanical stress.