Novel Test Structures for 3D NAND Array Plasma Damage Monitoring

The innovative test structure introduced in this work stems from a specific need to develop an electrical proxy to monitor charge damage induced by the processing of 3DNAND arrays. For the first time, the gates of the NHV and NLV transistor were connected to a portion of the array acting as an antenna. The findings show that, as expected from the literature, the failure mode depends on the thickness of the gate oxide. NHV transistors show charge trapping and no gate leakage, while NLV transistors are heavily damaged with high gate leakage but showing a threshold in the target (SILC - Stress Induced Leakage current). This work demonstrated that by incorporating an appropriate sensor structure, changes in electrical characteristics due to plasma interactions can be detected, to monitor array PID.