PARS Latch: A Power-Efficient and Resilient Latch for Mitigating Single-Event Multiple Upsets in Cyber-Physical Environments

Trends toward sub- 100 nm CMOS technology cause higher susceptibility of circuits to soft errors. Soft error occurrences in the circuits become an important issue not only in space applications but also at ground level. In the context of Industrial Cyber-Physical Systems (ICPS), such errors pose critical challenges in ensuring the reliability and energy efficiency of interconnected and automated systems. Adding redundancies to prevent these errors results in more power consumption, which is a critical issue in battery-based or energy-constrained ICPS applications. We proposed a latch in this paper which can mask all Single Event Transients (SETs), Single Event Upsets (SEUs), and multiple node upsets by using a state-hold element called C-Element. Moreover, the power consumption of the proposed latch has been diminished by the adaptive body bias method. SPICE simulations indicate that the proposed latch can mask 100% of SEUs and multiple node upsets while providing high reliability compared to other wellknown latches. The delay element used to filter SETs can produce up to 256ps delay. These are achieved with only 89% of the power overhead relative to the reference latch. Additionally, the adaptive body bias method has reduced power consumption by more than 40%.