Power switch improvement for RO array characterization in 18nm FD-SOI technology platform validation

We compare two power switches architectures implemented within test chips (18nm FD-SOI) that provide DUT selection in ring oscillators (RO) array, used for technology platform characterization. We first show the performance of a classic switch made of two pmos. Next, we illustrate that this design is largely improved by adding a third pmos and a nmos. We provide extensive data to show that the newer design has a much lower parasitic leakage, improves precision and enlarges temperature-voltage range.