Evaluation of Rapid Vt Testing of Wafer-Level MOSFETs

We evaluate applicability of a spot Ids method of rapid Vt test to wafer-level CMOS transistor testing. We discuss reference data requirements vs V<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ds</inf> bias, body bias, and W/L sizes with respect to Vt error. We compare Rapid Vt to full V<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">gs</inf> sweep Vt values on CMOS wafer NMOS and PMOS transistors and demonstrate comparable channel doping results.