Reducing Short-Circuit Current of CMOS Inverter Circuits with “PN-Body Tied SOI-FET”

We experimentally confirmed that the steep subthreshold slope (SS) device “PN body-tied silicon-on-insulator (SOI) field-effect transistor” can reduce the short-circuit current of a complementary metal-oxide semiconductor (CMOS) inverter. When the NMOS and PMOS steep SS positions overlap, they exhibit nearly right-angled transfer characteristics compared to conventional SOI CMOS. In this situation, the short-circuit current was also observed to be very small. This result confirms the possibility of achieving nearly zero short-circuit current in devices with steep SS.

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Publication Details

Published
2025-03-24
DOI
https://doi.org/10.1109/icmts63811.2025.11068915
Primary Topic
Advancements in Semiconductor Devices and Circuit Design
Type
article
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article

Reducing Short-Circuit Current of CMOS Inverter Circuits with “PN-Body Tied SOI-FET”

Takayuki Mori, Jiro Ida, Kazuki Nakahashi
Advancements in Semiconductor Devices and Circuit Design
article

Reducing Short-Circuit Current of CMOS Inverter Circuits with “PN-Body Tied SOI-FET”

Takayuki Mori, Jiro Ida, Kazuki Nakahashi
article en

Abstract

We experimentally confirmed that the steep subthreshold slope (SS) device “PN body-tied silicon-on-insulator (SOI) field-effect transistor” can reduce the short-circuit current of a complementary metal-oxide semiconductor (CMOS) inverter. When the NMOS and PMOS steep SS positions overlap, they exhibit nearly right-angled transfer characteristics compared to conventional SOI CMOS. In this situation, the short-circuit current was also observed to be very small. This result confirms the possibility of achieving nearly zero short-circuit current in devices with steep SS.

Kanazawa Institute of Technology (JP)
Affordable and clean energy
Openalex Percentile: Top 85%
Advancements in Semiconductor Devices and Circuit Design
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