Reducing Short-Circuit Current of CMOS Inverter Circuits with “PN-Body Tied SOI-FET”
We experimentally confirmed that the steep subthreshold slope (SS) device “PN body-tied silicon-on-insulator (SOI) field-effect transistor” can reduce the short-circuit current of a complementary metal-oxide semiconductor (CMOS) inverter. When the NMOS and PMOS steep SS positions overlap, they exhibit nearly right-angled transfer characteristics compared to conventional SOI CMOS. In this situation, the short-circuit current was also observed to be very small. This result confirms the possibility of achieving nearly zero short-circuit current in devices with steep SS.
Authors
- Takayuki Mori (ORCID: https://orcid.org/0000-0002-9199-0868)
- Jiro Ida
- Kazuki Nakahashi
Institutions
- Kanazawa Institute of Technology (JP)
Publication Details
- Published
- 2025-03-24
- DOI
- https://doi.org/10.1109/icmts63811.2025.11068915
- Primary Topic
- Advancements in Semiconductor Devices and Circuit Design
- Type
- article
- Field-Weighted Citation Impact
- 0.00