D-Mode GaN/AlGaN/GaN MOS-HEMT Test Structures for Evaluating Gate Dielectric Impact on Device Performance

This study presents a set of standardized test structures designed to systematically investigate the influence of gate dielectric materials on depletion-mode GaN/AlGaN/GaN MOS-HEMTs. By employing D-mode HEMTs, transfer length method (TLM) structures, and MOS capacitor structures, comprehensive characterization of essential device parameters, including maximum drain current (I<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">D,MAX</inf>), threshold voltage (V<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">TH</inf>), transconductance (G<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">M,MAX</inf>), subthreshold swing (SS), interface trap density (D<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">IT</inf>), and field-effect mobility (μ<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">FE</inf>) was conducted. Three distinct gate dielectrics (HfO<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</inf>, Al<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</inf>O<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</inf>, and SiNx) were analyzed, revealing clear correlations among dielectric properties, interface quality, and overall device performance. The integrated approach demonstrated the importance of optimized dielectric deposition and interface engineering, highlighting that despite the superior capacitance of high-κ dielectrics like HfO<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</inf>, interface quality critically influences device performance. This test-bed approach offers a powerful platform for systematically investigating and optimizing gate dielectric integration processes, advancing the development of high-performance GaN-based MOS-HEMT technologies.