An ISO 11784/5 Compliant Analysis for a Mixedsignal ASIC, for Animal RFID Readers' Frontends

In this work a custom integrated circuit is presented, aimed at implementing a low-cost and high-performance RFID reader for the cattle industry. It was designed to be fully compatible with the ISO 11784/85 standard for animal ID @ 134.2kHz. Firstly, the reader-tag link was characterized and an adequate system topology was proposed. Then, an initial version of the analog RFID front-end was implemented using discrete electronic components, and tested. Using these measurement results, an AD conversion stage, and subsequent digital filters, were optimized in a second, mixed-signal version, of the RFID reader engine to be implemented in an ASIC. The complete reader circuit was designed in a <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$0.18 \mu {m}$</tex> CMOS-HV technology including an analog front-end and programmable digital IIR filters, that can be adapted for both HDX and FDX ISO RFID tags. The resulting circuit occupies an area of less than <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$1.0 {mm}^{2}$</tex>.

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Publication Details

Published
2024-09-26
DOI
https://doi.org/10.1109/cafe63183.2024.11069323
Primary Topic
RFID technology advancements
Type
article
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article

An ISO 11784/5 Compliant Analysis for a Mixedsignal ASIC, for Animal RFID Readers' Frontends

Alfredo Arnaud, Matías Miguez, Joel Gak, Lucio Barbieri et al.
RFID technology advancements
article

An ISO 11784/5 Compliant Analysis for a Mixedsignal ASIC, for Animal RFID Readers' Frontends

Alfredo Arnaud, Matías Miguez, Joel Gak, Lucio Barbieri, Santiago Pinheiro
article en

Abstract

In this work a custom integrated circuit is presented, aimed at implementing a low-cost and high-performance RFID reader for the cattle industry. It was designed to be fully compatible with the ISO 11784/85 standard for animal ID @ 134.2kHz. Firstly, the reader-tag link was characterized and an adequate system topology was proposed. Then, an initial version of the analog RFID front-end was implemented using discrete electronic components, and tested. Using these measurement results, an AD conversion stage, and subsequent digital filters, were optimized in a second, mixed-signal version, of the RFID reader engine to be implemented in an ASIC. The complete reader circuit was designed in a <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$0.18 \mu {m}$</tex> CMOS-HV technology including an analog front-end and programmable digital IIR filters, that can be adapted for both HDX and FDX ISO RFID tags. The resulting circuit occupies an area of less than <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$1.0 {mm}^{2}$</tex>.

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RFID technology advancements
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