A 10‐Bit 120‐MS/s SAR ADC With Intermediate‐Voltage Dynamic Comparator and Calibration Scheme for Quantitative Decoupling

ABSTRACT This article presents a successive approximation register (SAR) ADC that incorporates an intermediate‐voltage dynamic comparator and calibration scheme for quantitative decoupling. The background calibration process of an ADC often occupies the time allocated for quantization, thereby limiting the operational speed of the ADC. To mitigate this issue, a novel calibration timing scheme has been proposed that can effectively decouple the calibration process from the quantization phase by integrating two additional switches at the input of the comparator. Furthermore, to overcome the constraint imposed by the comparator on the quantization speed and precision of SAR ADCs, an intermediate‐voltage dynamic comparator architecture has been developed. Compared with traditional double tail dynamic comparator, this innovative design enhances performance by leveraging intermediate values to trigger comparison results, thereby achieving faster and more efficient comparison outcomes. The designed ADC is simulated using a 65‐nm CMOS technology and operates at a power supply voltage of 1.2 V. Post‐simulation results reveal that the ADC achieves a signal‐to‐noise and distortion ratio (SNDR) of 59.34 dB at a sampling frequency of 120 MHz. Additionally, the power consumption is measured at 1.18 mW, and the figure of merit (FOM ) is calculated to be 13.03 fJ/conv‐step.