Neural Architecture Search (NAS) for Auto-Configurable SoC Designs

The increasing complexity of System-on-Chip (SoC) designs necessitates advanced techniques for automating the configuration of heterogeneous computing resources. Neural Architecture Search (NAS), a subdomain of AutoML, has emerged as a powerful tool to optimize deep neural network architectures. In this paper, we propose a novel framework that integrates NAS into the design flow of Auto-Configurable SoC architectures. By combining design-space exploration (DSE) with hardware-aware NAS algorithms, the proposed approach enables automated customization of SoC components such as accelerators, memory hierarchy, and interconnects. Experimental results demonstrate that the NAS-driven SoC design achieves significant improvements in power, performance, and area (PPA) trade-offs compared to traditional hand-crafted configurations.

Authors

Publication Details

Journal
International Journal For Multidisciplinary Research
Published
2025-06-28
DOI
https://doi.org/10.36948/ijfmr.2025.v07i03.49273
Primary Topic
VLSI and Analog Circuit Testing
Type
article
Field-Weighted Citation Impact
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article

Neural Architecture Search (NAS) for Auto-Configurable SoC Designs

Shoban Mude
International Journal For Multidisciplinary Research
VLSI and Analog Circuit Testing
article

Neural Architecture Search (NAS) for Auto-Configurable SoC Designs

Shoban Mude
article en

Abstract

The increasing complexity of System-on-Chip (SoC) designs necessitates advanced techniques for automating the configuration of heterogeneous computing resources. Neural Architecture Search (NAS), a subdomain of AutoML, has emerged as a powerful tool to optimize deep neural network architectures. In this paper, we propose a novel framework that integrates NAS into the design flow of Auto-Configurable SoC architectures. By combining design-space exploration (DSE) with hardware-aware NAS algorithms, the proposed approach enables automated customization of SoC components such as accelerators, memory hierarchy, and interconnects. Experimental results demonstrate that the NAS-driven SoC design achieves significant improvements in power, performance, and area (PPA) trade-offs compared to traditional hand-crafted configurations.

International Journal For Multidisciplinary ResearchVol. 7(3)
Openalex Percentile: Top 84%
VLSI and Analog Circuit Testing
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