Block Processing-Based Diagonal Symmetry 2D FIR Filter Architecture Design Using OBC DA

D Finite Impulse Response (FIR) filters are desired to pre-processing the images. The optimization in architectures decreases the power consumption, area, and delay. Parallel processing can boost the throughput of 2D FIR filter topologies and reduce image processing clock cycles. The most complex blocks in the filter architecture are multipliers, but the symmetry in the coefficients trim quantity of multipliers. This paper proposes a Diagonal Symmetry Filter (DSF) with parallel processing. Next, an enhanced Distribute Arithmetic (DA) logic Offset Binary Coding (OBC)-based multiplication approach replaces the remaining multipliers of the filter architecture. The OBC-DA decreases LUT size, filter architecture area, power, and latency. Here, parallel processing, symmetry, and OBC-DA ideas enhance the 2D FIR Filter Structure (FS). The suggested architecture is realized on FPGA using Xilinx tools. To observe the improvement of the designed 2D FIR Filter Architecture (FA), general 2D FIR filter no symmetry and DA, and conventional DAbased 2D FIR filters were also realized and compared.