A Low Power Spiking Neural Network Accelerator on FPGA for Real-Time Edge Computing

Machine learning (ML) has become a cornerstone for innovative applications in the Internet of Things (IoT), such as intelligent security and autonomous systems. However, cloud-based ML solutions introduce latency, high power consumption, and privacy risks, making them unsuitable for real-time, resource-constrained IoT applications. Spiking Neural Networks (SNNs), with their low power consumption and biologically inspired computational efficiency, offer a promising alternative to traditional artificial neural networks (ANNs) in edge computing environments. Despite their potential, current SNN hardware accelerators are limited by scalability and power inefficiencies. This paper presents a co-optimization approach for both software and hardware to enhance the performance of SNNs in IoT applications. On the software side, we quantize weights to 8-bit fixed-point values and merge batch normalization layers to minimize computational overhead. On the hardware side, we design a frame-based SNN accelerator based on Leaky Integrate-and-Fire (LIF) neuron model, which reuses computational units and memory to improve resource efficiency. We also introduce a four-dimensional parallel computing architecture to enhance data processing speed and apply a bitmap-based sparse encoding method for weight storage, reducing memory and bandwidth requirements. Experimental results demonstrate that the proposed design significantly improves both the energy efficiency and real-time processing capabilities, which is more suitable for deployment in resource-constrained IoT devices.

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Publication Details

Published
2025-05-23
DOI
https://doi.org/10.1109/icaisisas64483.2025.11051374
Citations
1
Primary Topic
Advanced Memory and Neural Computing
Type
article
Field-Weighted Citation Impact
0.73

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A Low Power Spiking Neural Network Accelerator on FPGA for Real-Time Edge Computing

Jian Zhang, Yimao Cai, Yu Wang, Yanlong Zhang et al.
1 citations
Advanced Memory and Neural Computing
0.73
article

A Low Power Spiking Neural Network Accelerator on FPGA for Real-Time Edge Computing

Jian Zhang, Yimao Cai, Yu Wang, Yanlong Zhang, Qi-Liang Chen, Bo Bi
article en
1 citations

Abstract

Machine learning (ML) has become a cornerstone for innovative applications in the Internet of Things (IoT), such as intelligent security and autonomous systems. However, cloud-based ML solutions introduce latency, high power consumption, and privacy risks, making them unsuitable for real-time, resource-constrained IoT applications. Spiking Neural Networks (SNNs), with their low power consumption and biologically inspired computational efficiency, offer a promising alternative to traditional artificial neural networks (ANNs) in edge computing environments. Despite their potential, current SNN hardware accelerators are limited by scalability and power inefficiencies. This paper presents a co-optimization approach for both software and hardware to enhance the performance of SNNs in IoT applications. On the software side, we quantize weights to 8-bit fixed-point values and merge batch normalization layers to minimize computational overhead. On the hardware side, we design a frame-based SNN accelerator based on Leaky Integrate-and-Fire (LIF) neuron model, which reuses computational units and memory to improve resource efficiency. We also introduce a four-dimensional parallel computing architecture to enhance data processing speed and apply a bitmap-based sparse encoding method for weight storage, reducing memory and bandwidth requirements. Experimental results demonstrate that the proposed design significantly improves both the energy efficiency and real-time processing capabilities, which is more suitable for deployment in resource-constrained IoT devices.

Peking University (CN), Beijing Microelectronics Technology Institute (CN)
National Natural Science Foundation of China
Affordable and clean energy
Openalex Percentile: Top 26%
Advanced Memory and Neural Computing
0.73
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