An approximate model SpMV on FPGA assisting HLS optimizations for low power and high performance

<span>High performance computing (HPC) in embedded systems is particularly relevant with the rise of artificial intelligence (AI) and machine learning at the edge. Deep learning models require substantial computational power, and running these models on embedded systems with limited resources poses significant challenges. The energy-efficient nature of field-programmable gate arrays (FPGAs), coupled with their adaptability, positions them as compelling choices for optimizing the performance of sparse matrix-vector multiplication (SpMV), which plays a significant role in various computational tasks within these fields. This article initially did analysis to find a power and delay efficient SpMV model kernel using high level synthesis (HLS) optimizations which incorporates loop pipelining, varied memory access patterns, and data partitioning strategies, all of this exert influence on the underlying hardware architecture. After identifying the minimum resource utilization model, we propose an approximate model algorithm on SpMV kernel to reduce the execution time in Xilinx Zynq-7000 FPGA. The experimental results shows that the FPGA power consumption was reduced by 50% when compared to a previously implemented streaming dataflow engine (SDE) flow, and the proposed approximate model improved performance by 2× times compared to that of original compressed sparse row (CSR) sparse matrix.</span>