A Dual-Mode Compatible CT ADC With FIR DAC and SB Quantization for DSM and IDSM Operations

This paper presents a continuous-time (CT) ADC capable of operating as either a delta-sigma modulator (DSM) or an incremental DSM (IDSM). To address the high jitter sensitivity inherent to oversampled CT systems, an architecture incorporating FIR DACs and a single-bit (SB) quantizer is adopted. A fully numerical loop parameter extraction method based on the least-mean-square (LMS) algorithm is proposed, eliminating the need for tedious algebraic derivations required in conventional approaches. Additionally, a multirate state-space simulation framework is introduced to address compatibility issues arising from excess loop delay (ELD), which conventional approaches fail to adequately handle. At the circuit level, a compact and energy-efficient compensation FIR DAC is implemented based on a configurable capacitive passive summation network. The main FIR DAC with 8 taps employs a Zapped Virtual-Ground-Switched Dual Return-To-Open (DRTO) topology to suppress ISI and the effects of limited reference impedance. Layout asymmetry in the main FIR DAC induces differential-mode (DM) crosstalk, which is alleviated through a layout-level cancellation technique leveraging even-indexed FIR taps. The prototype, fabricated in a TSMC 65 nm LP CMOS process with a core area of 0.235 mm², achieves SNDR<sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">peak</sub> of 84.3 dB and 81.3 dB in DSM and IDSM modes, respectively, over a 100 kHz bandwidth. Powered by a single 1.2 V supply, it consumes 269 μW and 277 μW in DSM and IDSM modes, corresponding to FoMSNDR of 170 dB and 166.9 dB.