PUDTune: Multi-Level Charging for High-Precision Calibration in Processing-Using-DRAM

Recently, practical analog in-memory computing has been realized using unmodified commercial DRAM modules. The underlying Processing-Using-DRAM (PUD) techniques enable high-throughput bitwise operations directly within DRAM arrays. However, the presence of inherent error-prone columns hinders PUD's practical adoption. While selectively using only error-free columns would ensure reliability, this approach significantly reduces PUD's computational throughput. This paper presents PUDTune, a novel high-precision calibration technique for increasing the number of error-free columns in PUD. PUDTune compensates for errors by applying pre-identified column-specific offsets to PUD operations. By leveraging multi-level charge states of DRAM cells, PUDTune generates fine-grained and wide-range offset variations despite the limited available rows. Our experiments with DDR4 DRAM demonstrate that PUDTune increases the number of error-free columns by 1.81× compared to conventional implementations, improving addition and multiplication throughput by 1.88× and 1.89× respectively.

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Publication Details

Journal
IEEE Computer Architecture Letters
Published
2025-07-01
DOI
https://doi.org/10.1109/lca.2025.3585312
Primary Topic
VLSI and Analog Circuit Testing
Type
article
Field-Weighted Citation Impact
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article

PUDTune: Multi-Level Charging for High-Precision Calibration in Processing-Using-DRAM

Ting Cao, Tatsuya Kubo, Shinya Takamaeda-Yamazaki, Lei Qu et al.
IEEE Computer Architecture Letters
VLSI and Analog Circuit Testing
article

PUDTune: Multi-Level Charging for High-Precision Calibration in Processing-Using-DRAM

Ting Cao, Tatsuya Kubo, Shinya Takamaeda-Yamazaki, Lei Qu, Daichi Tokuda
article en

Abstract

Recently, practical analog in-memory computing has been realized using unmodified commercial DRAM modules. The underlying Processing-Using-DRAM (PUD) techniques enable high-throughput bitwise operations directly within DRAM arrays. However, the presence of inherent error-prone columns hinders PUD's practical adoption. While selectively using only error-free columns would ensure reliability, this approach significantly reduces PUD's computational throughput. This paper presents PUDTune, a novel high-precision calibration technique for increasing the number of error-free columns in PUD. PUDTune compensates for errors by applying pre-identified column-specific offsets to PUD operations. By leveraging multi-level charge states of DRAM cells, PUDTune generates fine-grained and wide-range offset variations despite the limited available rows. Our experiments with DDR4 DRAM demonstrate that PUDTune increases the number of error-free columns by 1.81× compared to conventional implementations, improving addition and multiplication throughput by 1.88× and 1.89× respectively.

IEEE Computer Architecture LettersVol. 24(2)
Microsoft Research Asia (China) (CN), The University of Tokyo (JP)
Affordable and clean energy
Openalex Percentile: Top 84%
VLSI and Analog Circuit Testing
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PUDTune: Multi-Level Charging for High-Precision Calibration in Processing-Using-DRAM — Ting Cao, Tatsuya Kubo, et al. · IEEE Computer Architecture Letters (2025) | TGRS Research Map | TGRS