PUDTune: Multi-Level Charging for High-Precision Calibration in Processing-Using-DRAM
Recently, practical analog in-memory computing has been realized using unmodified commercial DRAM modules. The underlying Processing-Using-DRAM (PUD) techniques enable high-throughput bitwise operations directly within DRAM arrays. However, the presence of inherent error-prone columns hinders PUD's practical adoption. While selectively using only error-free columns would ensure reliability, this approach significantly reduces PUD's computational throughput. This paper presents PUDTune, a novel high-precision calibration technique for increasing the number of error-free columns in PUD. PUDTune compensates for errors by applying pre-identified column-specific offsets to PUD operations. By leveraging multi-level charge states of DRAM cells, PUDTune generates fine-grained and wide-range offset variations despite the limited available rows. Our experiments with DDR4 DRAM demonstrate that PUDTune increases the number of error-free columns by 1.81× compared to conventional implementations, improving addition and multiplication throughput by 1.88× and 1.89× respectively.
Authors
- Ting Cao (ORCID: https://orcid.org/0000-0002-0596-578X)
- Tatsuya Kubo (ORCID: https://orcid.org/0009-0005-1523-3063)
- Shinya Takamaeda-Yamazaki (ORCID: https://orcid.org/0000-0003-3441-1695)
- Lei Qu
- Daichi Tokuda
Institutions
- Microsoft Research Asia (China) (CN)
- The University of Tokyo (JP)
Publication Details
- Journal
- IEEE Computer Architecture Letters
- Published
- 2025-07-01
- DOI
- https://doi.org/10.1109/lca.2025.3585312
- Primary Topic
- VLSI and Analog Circuit Testing
- Type
- article
- Field-Weighted Citation Impact
- 0.00