Hybrid Multi-Level Cell Spin-Orbit Torque Memory for Fast and Robust Memory Operations

This paper proposes a hybrid spintronic multi-level cell (MLC) optimized for fast and reliable memory operations. The proposed MLC employs two magnetic tunnel junctions with distinct magnetization characteristics within a single cell, leveraging their significant differences in critical current requirements to effectively mitigate write-disturb failures. Moreover, the proposed design incorporates a spin-orbit torque-based switching mechanism along with a device multiplexing architecture, which together enable a one-step write operation and an opportunistic one-step read operation. Simulations demonstrate up to a 2× reduction in latency compared to conventional spintronic MLCs, along with a 2× increase in area efficiency over single-level cell designs and a high write-disturb margin of 61%.