A Bit‐Serial Compute‐Transfer Architecture for High‐Speed Data Processing in Chip‐to‐Chip Systems

ABSTRACT This brief proposes a bit‐serial compute‐transfer architecture tailored for high‐speed data processing across chip‐to‐chip links. Our design merges computation and transmission at the physical layer via a voltage‐mode logic (VML) interface, without intermediate packing or unpacking. In SMIC 0.13 µm CMOS, the architecture achieves 1 Gbps per channel at 1 GHz, delivering 0.625 GOPS to resource‐constrained edge devices. While overall energy efficiency is lower than that of computing‐only designs, the proposed structure excels in area, gate density, and scalability. This compute‐transfer architecture reduces bandwidth bottlenecks and deserialization overhead in multi‐chip systems, offering a modular building block for future neural network accelerators.