Silicon‐Integrated Next‐Generation Plasmonic Devices for Energy‐Efficient Semiconductor Applications

Abstract Silicon (Si)‐based integrated photonics has demonstrated significant advances in miniaturization and performance, yet critical challenges remain in achieving efficient on‐chip communication at high bandwidths. This review asserts that next‐generation Si‐integrated plasmonics, particularly through advanced architectures like coupled hybrid plasmonic waveguides (CHPWs) and the strategic use of complementary metal–oxide–semiconductor (CMOS)‐compatible materials, offer a critical pathway to overcome these limitations. Plasmonic devices on Si and silicon‐on‐insulator (SOI) substrates enable subwavelength light confinement and enhanced light‐matter interactions through hybrid modes. However, integrating traditional plasmonic materials like gold (Au) and silver (Ag) into Si‐based platforms presents significant challenges, particularly due to their incompatibility with standard Si processing techniques and their increased optical losses at longer wavelengths, which can hinder performance in near‐infrared applications. Distinctively focusing on viable integration strategies, this review explores recent progress in Si‐integrated hybrid‐mode plasmonic devices, highlighting the potential of transparent conductive oxides (TCOs) like indium tin oxide (ITO) for low‐loss, tunable operation. Key device topologies, including CHPWs and dielectric‐based heterostructures, are examined in depth, alongside CMOS‐aligned fabrication techniques and practical considerations. By critically comparing various plasmonic approaches and identifying their respective advantages and limitations, a path toward realizing the full potential of plasmonics in shaping the future of high‐performance, Si‐based integrated photonics is charted.