Improving the reliability of SKINNY-Hash for IoT applications with less area-power overhead

The widespread adoption of Internet of Things (IoT) devices has significantly increased the demand for IoT applications, which rely extensively on data collection and network transmission. However, the reliability of these devices, especially regarding the security and privacy of the data they handle, is a significant concern. This issue is further complicated by their exposure to environmental radiation and vulnerability to natural faults and malicious attacks. Cryptographic algorithms are crucial for securing IoT devices, but ensuring their reliability in such challenging environments is difficult. This work introduces a concurrent error detection technique called Space Redundancy with Complement Operands (SRECO) to enhance the reliability of cryptographic algorithms used in IoT devices. The lightweight SKINNY-Hash is adopted for the study. Specifically, SRECO is applied to the SKINNY-128-256 block cipher. Furthermore, we implement a resource-sharing concept to minimize the area-power overhead in the function architecture of SKINNY-Hash caused by the SRECO architecture. The function architecture in SKINNY-Hash is described using Very Large-Scale Integrated Circuits Hardware Description Language (VHDL) and synthesized with the Genus synthesis tool by Cadence, generating area-power reports. ModelSim SE-64 is employed for behavioural verification of the function architecture. The area-power results of our proposed work are compared with the traditional Double Modular Redundancy (DMR) technique, demonstrating that our approach has a low area-power overhead.