SCALABLE LOGIC BIST DESIGN AND ANALYSIS FOR ENHANCED TESTING OF COMBINATIONAL CIRCUITS

The paper introduces a scalable Logic Built-In Self-Test (BIST) approach for combinational circuits, utilizing a Bit Swapping Linear Feedback Shift Register (BS-LFSR) as the test pattern generator.Unlike conventional Linear Feedback Shift Registers (LFSRs) that lead to increased dynamic power dissipation due to high switching activity, the BS-LFSR reduces the number of transitions, thereby improving power efficiency.The design and implementation were implemented using FPGA and Cadence 180nm technology.Comparative power analysis indicates that the BS-LFSR architecture significantly reduces power consumption compared to traditional LFSR systems.Delay analysis reveals that while pre-synthesis processing times are shorter, post-synthesis data propagation times increase, highlighting a trade-off between synthesis stages.Additionally, area analysis confirms a modest increase in footprint due to integrating a multiplexer in the BS-LFSR, but this is offset by overall enhancements in performance and efficiency.This study demonstrates the potential of BS-LFSR in enhancing the effectiveness of BIST in combinational circuits.