Desgin of Low Power Asynchronous SAR ADC in CMOS Technology

This project presents the design of a low power Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC) using asynchronous techniques.Traditional synchronous SAR ADCs suffer from clock-related power consumption and timing issues, especially at low sampling rates.By adopting an asynchronous architecture, this design eliminates the need for a global clock, thereby reducing dynamic power dissipation.The circuit employs event-driven control logic to trigger operations, resulting in improved energy efficiency.A capacitor-based DAC and a dynamic comparator are used to further minimize power usage.The proposed ADC achieves high resolution and low latency while maintaining a compact layout.Simulations are performed to validate the power-performance trade-offs.The design is suitable for low-power applications such as biomedical devices and IoT sensors.The project demonstrates how asynchronous design can significantly enhance SAR ADC efficiency for modern low-energy systems.