Design of Novel CMOS Current-Mode Multi-Operand Adder Low Power Encoder Design

As a fundamental arithmetic module, the adder is not only utilized independently but also serves as a critical component in operations such as multiplication, where its power consumption significantly impacts overall system efficiency. According to Kirchhoff's Current Law (KCL), the algebraic sum of currents entering and exiting any circuit node must equal zero, which inherently facilitates current-mode circuits in summation operations. However, in multi-bit multi-operand summation circuits, conventional discrete cascaded carry mechanisms generate substantial comparison currents during propagation, leading to excessive power dissipation. To address this limitation, this paper proposes a novel CMOS current-mode multi-operand adder that effectively suppresses cascaded carry-induced comparison currents. The proposed architecture demonstrates superior performance in single-bit multi-operand summation, achieving a 44.9% reduction in power consumption and a 28.5% decrease in transistor count compared to traditional current-mode adders. Furthermore, it enables multi-bit multi-operand summation through skip-carry cascading configurations. PSPICE simulations confirm the designed CMOS current-mode multi-operand adder exhibits correct logic functionality, simplified circuit topology, and significantly improved power efficiency.