A Sub-Sampling-Chopper PLL With Residual-Free Charge-Sharing Canceling Achieving 39-fs _rms Jitter and -258.2-dB FoM _J

This paper presents a sub-sampling-chopper (SSCPLL) that incorporates a chopper-stabilized phase detector (PD) and charge pump (CP), along with a novel low-power, residual-free charge-share-canceling (RF-CSC) scheme. It features: Firstly, a cross-coupled pre-charging across two chopping phases to fully nullify residual charge-sharing by compensating inter-cycle voltage differences. Secondly, a reset mechanism that minimizes charge compensation per clock cycle, reducing dynamic power consumption. Fabricated in 65-nm CMOS technology, the RF-SS-CPLL occupies an active area of 0.37mm2. Operating at 9-GHz with a 100 MHz reference input, it achieves 39-fs integrated jitter (1 kHz-100 MHz) and -69.78dBc reference spurs, yielding a jitter-power figure of merit (FoMJ) of -258.24dB.