An Innovative Method to Enhance PLL Resolution in Synchronized Embedded Systems

Modern system on a chips for embedded applications employ integrated Phased Locked Loop (PLL) circuits to synthesize clock signals for themselves for low-cost implementation by reducing part count. Such integrated PLLs can be found in microcontrollers (MCU), application processors (AP) and field-programmable gate arrays (FPGA), for example. They offer remarkable capabilities, like fractional tuning, wide code word registers, and the possibility of run-time configuration. These features are quite similar to the capabilities of dedicated PLL circuits used in distributed synchronous measurement and control systems utilizing IEEE 1588 for coherent sampling. Therefore, it is reasonable to investigate how these built in PLL circuits can be utilized in synchronous measurement and control systems to reduce cost by omitting the dedicated PLL. This paper presents this investigation and proposes a dithering algorithm to improve the frequency resolution of the integrated PLL, as the frequency resolution of these integrated PLLs is found to be to limiting factor. The proposed solution allows finer grained synchronization in embedded system by modifying the firmware of the embedded system with little or no hardware modification, so it is not only applicable to new designs but existing products can be improved by firmware update. The proposed solution and the achievable performance are also demonstrated by an actual IEEE 1588 compliant embedded system with practical measurements proving the applicability of our approach.